參數(shù)資料
型號： MPC8567ECVTAUJJA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1333 MHz, RISC PROCESSOR, PBGA1023
封裝： 33 X 33 MM, 2.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-1023
文件頁數(shù)： 85/139頁
文件大?。?/td> 1449K
代理商： MPC8567ECVTAUJJA
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
5
MPC8568E Overview
— Three 1-Gbps Ethernet interfaces using three GMII, two RGMII/TBI/RTBI
— Up to eight 10/100-Mbps Ethernet interfaces using MII or RMII
— Up to eight T1/E1/J1/E3 or DS-3 serial interfaces
1.2.4
Integrated Security Engine (SEC)
The SEC is a modular and scalable security core optimized to process all the algorithms associated with
IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP. Although it is not a protocol processor, the SEC is
designed to perform multi-algorithmic operations (for example, 3DES-HMAC-SHA-1) in a single pass of
the data. The version of the SEC used in the MPC8568E is specifically capable of performing single-pass
security cryptographic processing for SSL 3.0, SSL 3.1/TLS 1.0, IPSec, SRTP, and 802.11i.
Optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and
3GPP
Compatible with code written for the Freescale MPC8541E and MPC8555E devices
XOR engine for parity checking in RAID storage applications.
Four crypto-channels, each supporting multi-command descriptor chains
Cryptographic execution units:
— PKEU—public key execution unit
— DEU—Data Encryption Standard execution unit
— AESU—Advanced Encryption Standard unit
— AFEU—ARC four execution unit
— MDEU—message digest execution unit
— KEU—Kasumi execution unit
— RNG—Random number generator
1.2.5
Enhanced Three-Speed Ethernet Controllers
The MPC8568E has two on-chip enhanced three-speed Ethernet controllers (eTSECs). The eTSECs
incorporate a media access control (MAC) sublayer that supports 10- and 100-Mbps and 1-Gbps
Ethernet/802.3 networks with MII, RMII, GMII, RGMII, TBI, and RTBI physical interfaces. The eTSECs
include 2-Kbyte receive and 10-Kbyte transmit FIFOs and DMA functions.
The MPC8568E eTSECs support programmable CRC generation and checking, RMON statistics, and
jumbo frames of up to 9.6 Kbytes. Frame headers and buffer descriptors can be forced into the L2 cache
to speed classification or other frame processing. They are IEEE Std 802.3, IEEE 802.3u, IEEE 802.3x,
IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab-compatible.
The buffer descriptors are based on the MPC8260 and MPC860T 10/100 Ethernet programming models.
Each eTSEC can emulate a PowerQUICC III TSEC, allowing existing driver software to be re-used with
minimal change.
Some of the key features of these controllers include:
Flexible configuration for multiple PHY interface configurations. Table 1 lists available
configurations.
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