參數(shù)資料
型號： MPC8567ECVTAUJJA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1333 MHz, RISC PROCESSOR, PBGA1023
封裝： 33 X 33 MM, 2.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-1023
文件頁數(shù)： 101/139頁
文件大?。?/td> 1449K
代理商： MPC8567ECVTAUJJA
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
64
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
Figure 40. Receiver of SerDes Reference Clocks
13.2.2
DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the MPC8568E SerDes reference clock inputs is different depending on the
signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described
below.
Differential Mode
— The input amplitude of the differential clock must be between 400mV and 1600mV differential
peak-peak (or between 200mV and 800mV differential peak). In other words, each signal wire
of the differential pair must have a single-ended swing less than 800mV and greater than
200mV. This requirement is the same for both external DC-coupled or AC-coupled connection.
— For external DC-coupled connection, as described in section 13.2.1, the maximum average
current requirements sets the requirement for average voltage (common mode voltage) to be
between 100 mV and 400 mV. Figure 41 shows the SerDes reference clock input requirement
for DC-coupled connection scheme.
— For external AC-coupled connection, there is no common mode voltage requirement for the
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
SCOREGND. Each signal wire of the differential inputs is allowed to swing below and above
the command mode voltage (SCOREGND). Figure 42 shows the SerDes reference clock input
requirement for AC-coupled connection scheme.
Single-ended Mode
— The reference clock can also be single-ended. The SD_REF_CLK input amplitude
(single-ended swing) must be between 400mV and 800mV peak-peak (from Vmin to Vmax)
with SD_REF_CLK either left unconnected or tied to ground.
— The SD_REF_CLK input average voltage must be between 200 and 400 mV. Figure 43 shows
the SerDes reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or
AC-coupled externally. For the best noise performance, the reference of the clock could be DC
Input
Amp
50
Ω
50
Ω
SD_REF_CLK
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