參數(shù)資料
型號: MPC8560PXAPDB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 833 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件頁數(shù): 39/108頁
文件大?。?/td> 2170K
代理商: MPC8560PXAPDB
MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1
36
Freescale Semiconductor
Figure 15 shows the MII management AC timing diagram.
Figure 15. MII Management Interface Timing Diagram
MDC fall time
tMDHF
10
ns
4
Notes:
1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX
symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are
invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data
input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup
time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.This parameter is dependent on the system clock speed (that is, for a system clock of 267 MHz, the maximum frequency
is 8.3 MHz and the minimum frequency is 1.2 MHz; for a system clock of 333 MHz, the maximum frequency is
10.4 MHz and the minimum frequency is 1.5 MHz).
3.This parameter is dependent on the system clock speed (that is, for a system clock of 267 MHz, the delay is 60 ns and
for a system clock of 333 MHz, the delay is 48 ns).
4.Guaranteed by design.
Table 28. MII Management AC Timing Specifications (continued)
At recommended operating conditions with OVDD is 3.3 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Notes
MDC
tMDDXKH
tMDC
tMDCH
tMDCR
tMDCF
tMDDVKH
tMDKHDX
MDIO
(Input)
(Output)
tMDKHDV
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