參數(shù)資料
型號(hào)： MPC8560PX833LC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 833 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, PLASTIC, FCBGA-783
文件頁(yè)數(shù)： 18/104頁(yè)
文件大?。?/td> 1244K
代理商： MPC8560PX833LC
MPC8560 Integrated Processor Hardware Specifications, Rev. 5
20
Freescale Semiconductor
DDR SDRAM
MCK[n] duty cycle
tMCKH/tMCK
45
55
%
8
ADDR/CMD output valid
tDDKHOV
—3
ns
4, 9
ADDR/CMD output invalid
tDDKHOX
1—
ns
4, 9
Write CMD to first MDQS capture edge
tDDSHMH
tMCK + 1.5
tMCK + 4.0
ns
5
MDQ/MECC/MDM output setup with respect to
MDQS
333 MHz
266 MHz
200 MHz
tDDKHDS,
tDDKLDS
900
1100
1200
—ps
6, 9
MDQ/MECC/MDM output hold with respect to
MDQS
333 MHz
266 MHz
200 MHz
tDDKHDX,
tDDKLDX
900
1100
1200
—ps
6, 9
MDQS preamble start
tDDSHMP
0.75
× tMCK + 1.5
0.75
× tMCK + 4.0
ns
7, 8
MDQS epilogue end
tDDSHME
1.5
4.0
ns
7, 8
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (OX or DX). For example,
tDDKHOV symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(O) are valid (V) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. Maximum possible clock skew between a clock MCK[n] and its relative inverse clock MCK[n], or between a clock MCK[n] and
a relative clock MCK[m] or MSYNC_OUT. Skew measured between complementary signals at GVDD/2.
4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK and MDQ/MECC/MDM/MDQS.
5. Note that tDDSHMH follows the symbol conventions described in note 1. For example, tDDSHMH describes the DDR timing (DD)
from the rising edge of the MSYNC_IN clock (SH) until the MDQS signal is valid (MH). tDDSHMH can be modified through
control of the DQSS override bits in the TIMING_CFG_2 register. These controls allow the relationship between the
synchronous clock control timing and the source-synchronous DQS domain to be modified by the user. For best turnaround
times, these may need to be set to delay tDDSHMH an additional 0.25tMCK. This will also affect tDDSHMP and tDDSHME
accordingly. See the MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual for a description
and understanding of the timing modifications enabled by use of these bits.
6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the device.
7. All outputs are referenced to the rising edge of MSYNC_IN (S) at the pins of the device. Note that tDDSHMP follows the symbol
conventions described in note 1. For example, tDDSHMP describes the DDR timing (DD) from the rising edge of the MSYNC_IN
clock (SH) for the duration of the MDQS signal precharge period (MP).
8. Guaranteed by design.
9. Guaranteed by characterization.
Table 16. DDR SDRAM Output AC Timing Specifications–DLL Mode (continued)
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter
Symbol 1
Min
Max
Unit
Notes
相關(guān)PDF資料
PDF描述
MPC8560PXAQFD 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
MPC8560PX833LD 32-BIT, 833 MHz, RISC PROCESSOR, PBGA783
MPC8560PX833JB 32-BIT, 833 MHz, RISC PROCESSOR, PBGA783
MPC8560PXAQFB 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
MPC8560CPX667JD 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC8560PXAQFB 功能描述:微處理器 - MPU PQ 3 DRACO-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8560PXAQFC 功能描述:微處理器 - MPU PQ 3 DRACO-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8560VT667LB 功能描述:微處理器 - MPU PQ 3 8560-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8560VT667LC 功能描述:微處理器 - MPU PQ 3 8560-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8560VT833LB 功能描述:微處理器 - MPU PQ 3 8560-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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