參數(shù)資料
型號(hào): MPC8560CPXALFB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件頁數(shù): 29/108頁
文件大?。?/td> 2170K
代理商: MPC8560CPXALFB
MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1
Freescale Semiconductor
27
Ethernet: Three-Speed, MII Management
Figure 7 shows the GMII transmit AC timing diagram.
Figure 7. GMII Transmit AC Timing Diagram
7.2.1.2 GMII Receive AC Timing Specifications
Table 21 provides the GMII receive AC timing specifications.
GTX_CLK data clock fall time (80%-20%)
tGTXF
2
1.0
ns
Notes:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tGTKHDV symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state
(H) relative to the time date input signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX
symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative
to the time date input signals (D) going invalid (X) or hold time. Note that, in general, the clock reference symbol
representation is based on three letters representing the clock of a particular functional. For example, the subscript
of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
2.Guaranteed by design.
Table 21. GMII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Input low voltage
VIL
0.7
V
Input high voltage
VIH
1.9
V
RX_CLK clock period
tGRX
8.0
ns
RX_CLK duty cycle
tGRXH/tGRX
40
60
ns
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
tGRDVKH
2.0
ns
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
tGRDXKH
0.5
ns
RX_CLK clock rise (20%-80%)
tGRXR
2
1.0
ns
Table 20. GMII Transmit AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
GTX_CLK
TXD[7:0]
tGTKHDX
tGTX
tGTXH
tGTXR
tGTXF
tGTKHDV
TX_EN
TX_ER
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