參數(shù)資料
型號(hào)： MPC855
廠商： Motorola, Inc.
英文描述： Family Hardware Specifications
中文描述： 家庭硬件規(guī)格
文件頁(yè)數(shù)： 33/76頁(yè)
文件大?。?/td> 857K
代理商： MPC855
MOTOROLA
MPC860 Family Hardware Specifications
33
Bus Signal Timing
Figure 9-21. Asynchronous External Master—Control Signals Negation Timing
Table 9-7 provides interrupt timing for the MPC860.
Figure 9-22 provides the interrupt detection timing for the external level-sensitive lines.
Figure 9-22. Interrupt Detection Timing for External Level Sensitive Lines
Figure 9-23 provides the interrupt detection timing for the external edge-sensitive lines.
Table 9-7. Interrupt Timing
Num
Characteristic
1
1
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference
to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has
no direct relation with the total system interrupt latency that the MPC860 is able to support.
All Frequencies
Unit
Min
Max
I39
IRQx valid to CLKOUT rising edge (setup time)
6.00
—
ns
I40
IRQx hold time after CLKOUT
2.00
—
ns
I41
IRQx pulse width low
3.00
—
ns
I42
IRQx pulse width high
3.00
—
ns
I43
IRQx edge-to-edge time
4
×
T
CLOCKOUT
—
—
AS
CSx, WE[0:3],
OE, GPLx,
BS[0:3]
B43
CLKOUT
IRQx
I39
I40
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