參數(shù)資料
型號： MPC8379ECVRAGDA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689
封裝： 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù)： 89/114頁
文件大小： 1337K
代理商： MPC8379ECVRAGDA
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
76
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50
Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
Table 67 describes some AC parameters common to SATA protocols.
Figure 57. Differential Measurement Points for Rise and Fall Time
Figure 58. Single-Ended Measurement Points for Rise and Fall Time Matching
Table 67. SerDes Reference Clock Common AC Parameters
At recommended operating conditions with XVDD_SRDS or XVDD_SRDS = 1.0 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Rising Edge Rate
Rise Edge Rate
1.0
4.0
V/ns
Falling Edge Rate
Fall Edge Rate
1.0
4.0
V/ns
Differential Input High Voltage
VIH
200
—
mV
Differential Input Low Voltage
VIL
—
–200
mV
Rising edge rate (SD
n_REF_CLK) to falling edge rate
(SD
n_REF_CLK) matching
Rise-Fall Matching
—
20
%
Note:
1 Measurement taken from single ended waveform.
2 Measurement taken from differential waveform.
3 Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 57.
4 Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a
200 mV window centered on the median cross point where SDn_REF_CLK rising meets SD
n_REF_CLK falling. The median
cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge
Rate of SD
n_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference
should not exceed 20% of the slowest edge rate. See Figure 58.
VIH = +200 mV
0.0 V
VIL = –200 mV
SD
n_REF_CLK
Minus
SD
n_REF_CLK
Rise Edge Rate
Fall Edge Rate
TFALL TRISE
SD
n_REF_CLK
VCROSS MEDIAN
SD
n_REF_CLK
SD
n_REF_CLK
VCROSS MEDIAN
SD
n_REF_CLK
VCROSS MEDIAN –100 mV
VCROSS MEDIAN +100 mV
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