參數(shù)資料
型號: MPC8379ECVRAGDA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689
封裝: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù): 61/114頁
文件大小: 1337K
代理商: MPC8379ECVRAGDA
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
50
Freescale Semiconductor
JTAG
11.3.2.1
High-Speed Read Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
tCLK_DELAY + tDATA_DELAY + tODLY + tSHSIVKH < 1.5 × tSHSCK
tCLK_DELAY + tDATA_DELAY < 1.5 × tSHSCK tODLY tSHSIVKH
This means that Data + Clock delay can be up to 11 ns for a 20 ns clock cycle:
tCLK_DELAY + tDATA_DELAY < 30 14 5
tCLK_DELAY + tDATA_DELAY < 11
11.3.2.2
High-Speed Read Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
0.5
× t
SHSCK < tCLK_DELAY + tDATA_DELAY + tOH tSHSIXKH + tINT_CLK_DLY
0.5
× tSHSCK tOH + tSHSIXKH tINT_CLK_DLY < tCLK_DELAY + tDATA_DELAY
This means that Data + Clock delay must be greater than ~6 ns for a 20 ns clock cycle:
10 2.5 + (-1.5) < tCLK_DELAY + tDATA_DELAY
6 < tCLK_DELAY + tDATA_DELAY
11.3.2.3
High-Speed Read Combined Formula
The following equation is the combined formula to calculate the propagation delay range of the SD_CLK
and SD_DAT/CMD signals on the PCB.
0.5
× tSHSCK tOH + tSHSIXKH < tCLK_DELAY + tDATA_DELAY < 1.5 × tSHSCK tODLY tSHSIVKH
12 JTAG
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of
the MPC8379E.
12.1
JTAG DC Electrical Characteristics
Table 43 provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface of the
MPC8379E.
Table 43. JTAG interface DC Electrical Characteristics
Parameter
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—2.5
OVDD +0.3
V
Input low voltage
VIL
—–0.3
0.8
V
Input current
IIN
——
±30
μA
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