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參數(shù)資料
| 型號： | MPC8379ECVRAGDA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689 |
| 封裝： | 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689 |
| 文件頁數(shù)： | 21/114頁 |
| 文件大小： | 1337K |
| 代理商： | MPC8379ECVRAGDA |
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MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
14
Freescale Semiconductor
RESET Initialization
4.2
AC Electrical Characteristics
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. Table 8 provides the clock input
(CLKIN/PCI_CLK) AC timing specifications for the device.
5
RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8379E.
5.1
RESET DC Electrical Characteristics
Table 9 provides the DC electrical characteristics for the RESET pins of the device.
Table 8. CLKIN AC Timing Specifications
Parameter
Symbol
Min
Typical
Max
Unit
Notes
CLKIN/PCI_CLK frequency
fCLKIN
25
—
66.666
MHz
CLKIN/PCI_CLK cycle time
tCLKIN
15
—
40
ns
—
CLKIN/PCI_CLK rise and fall time
tKH, tKL
0.6
1.0
2.3
ns
CLKIN/PCI_CLK duty cycle
tKHK/tCLKIN
40
—
60
%
CLKIN/PCI_CLK jitter
—
± 150
ps
Notes:
1 Caution: The system, core and security block must not exceed their respective maximum or minimum operating frequencies.
2 Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.
3 Timing is guaranteed by design and characterization.
4 This represents the total input jitter-short term and long term-and is guaranteed by design.
5 The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
6 Spread spectrum is allowed up to 1% down-spread on CLKIN/PCI_CLK up to 60 KHz.
Table 9. RESET Pins DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
——
± 30
μA
Output high voltage
VOH
IOH = –8.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Note:
This table applies for pins PORESET and HRESET. The PORESET is input pin, thus stated output voltages are not relevant.
HRESET and SRESET are open drain pin, thus VOH is not relevant for these pins.
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