參數(shù)資料
型號(hào): MPC8378VRANGA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
封裝: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù): 46/125頁
文件大小: 894K
代理商: MPC8378VRANGA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
27
Change in VOS between “0” and
“1”
VOS
——
25
mV
Output current on short to GND
ISA, ISB
——
40
mA
Notes:
1. This will not align to DC-coupled SGMII. XVDD_SRDS-Typ =1.0 V.
2. |VOD|=|VSD_TXn -VSD_TXn|. |VOD| is also referred as output differential peak voltage. VTX-DIFFp-p =2 |VOD|.
3. The |VOD| value shown in the table assumes the following transmit equalization setting in SRDSnCR0[DDPA] and
SRDSnCR0[TXEQA] for lane A, and SRDSnCR0[DDPE] and SRDSnCR0[TXEQE] for lane E.
4. DPPA or DPPE bit is set to zero (selecting the full VDD-DIFF-p-p amplitude – power up default);
5. TXEQA or TXDQE is set based on the equalization setting shown in table.
6. VOS is also referred to as output common mode voltage.
7. The |VOD| value shown in the Typ column is based on the condition of XVDD_SRDS-Typ = 1.0 V, no common mode offset
variation (VOS = 500 mV), SerDes1 transmitter is terminated with 100- differential load between SD_TXn and SD_TXn.
Table 27. SGMII DC Receiver Electrical Characteristics
Parameter
Symbol
Min
Typical
Max
Unit
Note
Supply voltage
(L1_SDAVDD_0, L1_XCOREVDD)
XVDD_SRDS
0.95
1.0
1.05
V
DC input voltage range
N/A
1
Input differential voltage
SEICx = 01
SEICx = 00
VRX_DIFFp-p
100
175
—1200
mV
2, 4
Loss of signal threshold
SEICx = 01
SEICx = 00
VLOS
30
65
100
175
mV
3, 4
Input AC common mode voltage
VCM_ACp-p
100
mV
5
Receiver differential input
impedance
ZRX_DIFF
80
100
120
Receiver common mode input
impedance
ZRX_CM
20
35
Common mode input voltage
VCM
—Vxcorevss
—V
6
Notes:
1. Input must be externally AC-coupled.
2. VRX_DIFFp-p is also referred to as peak to peak input differential voltage.
3. The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in PCI Express. Refer to PCI
Express Differential Receiver (RX) Input Specifications section for further explanation.
4. The SEICx shown in the table refers to SRDSnCR[SEICA] for lane A and SRDSnCR[SEICE] for lane E.
5. VCM_ACp-p is also referred to as peak to peak AC common mode voltage.
6. On-chip termination to SGND_SRDSn (xcorevss).
Table 26. SGMII DC Transmitter Electrical Characteristics (continued)
Parameter
Symbol
Min
Typ
Max
Unit
Note
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