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參數(shù)資料
| 型號(hào)： | MPC8378VRANGA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689 |
| 封裝： | 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689 |
| 文件頁數(shù)： | 31/125頁 |
| 文件大?。?/td> | 894K |
| 代理商： | MPC8378VRANGA |
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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
13
4
Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8378E. Note that the
PCI_CLK/PCI_SYNC_IN signal or CLKIN signal is used as the PCI input clock depending on whether the device is configured
as a host or agent device. CLKIN is used when the device is in host mode.
4.1
DC Electrical Characteristics
The following table provides the clock input (CLKIN/PCI_CLK) DC timing specifications for the device.
4.2
AC Electrical Characteristics
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is
configured in PCI host or PCI agent mode. The following table provides the clock input (CLKIN/PCI_CLK) AC timing
specifications for the device.
Table 7. CLKIN DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
Note
Input high voltage
—
VIH
2.7
OVDD + 0.3
V
Input low voltage
—
VIL
–0.3
0.4
V
CLKIN Input current
0 V
V
IN OVDD
IIN
—± 10
A—
PCI_CLK Input current
0 V
V
IN 0.5 V or
OVDD – 0.5 V VIN OVDD
IIN
—± 30
A—
Note:
1. In PCI agent mode, this specification does not comply with PCI 2.3 Specification.
Table 8. CLKIN AC Timing Specifications
Parameter
Symbol
Min
Typical
Max
Unit
Note
CLKIN/PCI_CLK frequency
fCLKIN
25
—
66.666
MHz
CLKIN/PCI_CLK cycle time
tCLKIN
15
—
40
ns
—
CLKIN/PCI_CLK rise and fall time
tKH, tKL
0.6
1.0
2.3
ns
CLKIN/PCI_CLK duty cycle
tKHK/tCLKIN
40
—
60
%
CLKIN/PCI_CLK jitter
—
± 150
ps
Notes:
1. Caution: The system, core and security block must not exceed their respective maximum or minimum operating frequencies.
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter-short term and long term-and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
6. Spread spectrum is allowed up to 1% down-spread on CLKIN/PCI_CLK up to 60 KHz.
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