參數(shù)資料
型號： MPC8378ECVRANFA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 333 MHz, MICROPROCESSOR, PBGA689
封裝： 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù)： 37/125頁
文件大小： 894K
代理商： MPC8378ECVRANFA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
19
6.2
DDR1 and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR1 and DDR2 SDRAM Input AC Timing Specifications
This table provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8 V.
This table provides the input AC timing specifications for the DDR1 SDRAM when GVDD(typ) = 2.5 V.
This table provides the input AC timing specifications for the DDR1 and DDR2 SDRAM interface.
6.2.2
DDR1 and DDR2 SDRAM Output AC Timing Specifications
This table shows the DDR1 and DDR2 SDRAM output AC timing specifications.
Table 18. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
Parameter
Symbol
Min
Max
Unit
AC input low voltage
VIL
—MVREF – 0.25
V
AC input high voltage
VIH
MVREF + 0.25
—
V
Table 19. DDR1 SDRAM Input AC Timing Specifications for 2.5-V Interface
Parameter
Symbol
Min
Max
Unit
AC input low voltage
VIL
—MVREF – 0.31
V
AC input high voltage
VIH
MVREF + 0.31
—
V
Table 20. DDR1 and DDR2 SDRAM Input AC Timing Specifications
Parameter
Symbol
Min
Max
Unit
Note
Controller skew for MDQS-MDQ/MECC/MDM
400 MHz data rate
333 MHz data rate
266 MHz data rate
tCISKEW
–500
–750
500
750
ps
1, 2
—
Note:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQSn and any corresponding bit that
will be captured with MDQSn. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the following equation: tDISKEW = ±[T/4 – |tCISKEW|] where T is the MCK clock period and |tCISKEW| is the
absolute value of tCISKEW.
3. This specification applies only to DDR2 interface.
Table 21. DDR1 and DDR2 SDRAM Output AC Timing Specifications
Parameter
Symbol1
Min
Max
Unit
Note
MCKn cycle time, MCKn/MCKn crossing
tMCK
510
ns
ADDR/CMD output setup with respect to MCK
400 MHz data rate
333 MHz data rate
266 MHz data rate
200 MHz data rate
tDDKHAS
1.95
2.40
3.15
4.20
—
ns
3, 7
相關PDF資料
PDF描述
MPC8378ECVRAJDA 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689
MPC8378EVRALFA 32-BIT, 333 MHz, MICROPROCESSOR, PBGA689
MPC8378VRAJGA 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
MPC8378CVRANFA 32-BIT, 333 MHz, MICROPROCESSOR, PBGA689
MPC8378VRALFA 32-BIT, 333 MHz, MICROPROCESSOR, PBGA689
相關代理商/技術參數(shù)
參數(shù)描述
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