參數(shù)資料
型號(hào): MPC8378ECVRANFA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 333 MHz, MICROPROCESSOR, PBGA689
封裝: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁(yè)數(shù): 110/125頁(yè)
文件大?。?/td> 894K
代理商: MPC8378ECVRANFA
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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
85
This figure shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC
levels of the clock driver are compatible with device SerDes reference clock input’s DC requirement.
Figure 62. Single-Ended Connection (Reference Only)
20.2.4
AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase
noise less than 100 KHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15 MHz
is filtered by the PLL. The most problematic phase noise occurs in the 1–15 MHz range. The source impedance of the clock
driver should be 50
to match the transmission line and reduce reflections which are a source of noise to the system.
This table describes some AC parameters common to SGMII and PCI Express protocols.
Table 67. SerDes Reference Clock Common AC Parameters
At recommended operating conditions with XVDD_SRDS or XVDD_SRDS = 1.0 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Note
Rising Edge Rate
Rise Edge Rate
1.0
4.0
V/ns
Falling Edge Rate
Fall Edge Rate
1.0
4.0
V/ns
50
50
SDn_REF_CLK
100
differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
Single-Ended CLK
Driver Chip
33
Total 50
Assume clock driver’s
output impedance is about 16
50
MPC8378E
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