參數(shù)資料
型號: MPC8378ECVRANFA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 333 MHz, MICROPROCESSOR, PBGA689
封裝: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù): 107/125頁
文件大?。?/td> 894K
代理商: MPC8378ECVRANFA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
82
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or AC-coupled
externally. For the best noise performance, the reference of the clock could be DC or AC-coupled into the unused
phase (SDn_REF_CLK) through the same source impedance as the clock input (SDn_REF_CLK) in use.
Figure 56. Differential Reference Clock Input DC Requirements (External DC-Coupled)
Figure 57. Differential Reference Clock Input DC Requirements (External AC-Coupled)
Figure 58. Single-Ended Reference Clock Input DC Requirements
20.2.3
Interfacing With Other Differential Signaling Levels
The following list provides information about interfacing with other differential signaling levels.
With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are HCSL (high-speed
current steering logic) compatible DC-coupled.
Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can be used but may
need to be AC-coupled due to the limited common mode input range allowed (100 mV to 400 mV) for DC-coupled
connection.
LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output
first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling.
SDn_REF_CLK
Vmax < 800 mV
Vmin > 0 V
100 mV < Vcm < 400 mV
200 mV < Input Amplitude or Differential Peak < 800 mV
SDn_REF_CLK
Vcm
200 mV < Input Amplitude or Differential Peak < 800 mV
150
Vmin > Vcm – 400m V
fdafdVmax < Vcm + 400 mV
Vmax < Vcm + 400 mV
SDn_REF_CLK
400 mV < SDn_REF_CLK Input Amplitude < 800 mV
0V
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