參數(shù)資料
型號(hào)： MPC8377EVRANGA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
封裝： 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù)： 75/124頁
文件大?。?/td> 1462K
代理商： MPC8377EVRANGA
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
54
Freescale Semiconductor
I
2C
13 I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8377E.
13.1
I2C DC Electrical Characteristics
Table 45 provides the DC electrical characteristics for the I2C interface of the MPC8377E.
13.2
I2C AC Electrical Specifications
Table 46 provides the AC timing parameters for the I2C interface of the device.
Table 45. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 165 mV.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage level
VIH
0.7
× OVDD
OVDD + 0.3
V
—
Input low voltage level
VIL
–0.3
0.3
× OVDD
V—
Low level output voltage
VOL
00.2
× OVDD
Output fall time from VIH(min) to VIL(max) with a bus capacitance
from 10 to 400 pF
tI2KLKV
20 + 0.1
× CB
250
ns
Pulse width of spikes which must be suppressed by the input filter
tI2KHKL
050
ns
Capacitance for each I/O pin
CI
—10
pF
—
Input current
(0 V
≤ VIN ≤ OVDD)
IIN
—± 30
μA4
Note:
1 Output voltage (open drain or open collector) condition = 3 mA sink current.
2 C
B = capacitance of one bus line in pF.
3 Refer to the MPC8379E PowerQUICC II Pro Integrated Host Processor Reference Manual for information on the digital filter
used.
4 I/O pins will obstruct the SDA and SCL lines if OV
DD is switched off.
Table 46. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 45).
Parameter
Symbol1
Min
Max
Unit
Notes
SCL clock frequency
fI2C
0
400
kHz
—
Low period of the SCL clock
tI2CL
1.3
—
μs—
High period of the SCL clock
tI2CH
0.6
—
μs—
Setup time for a repeated START condition
tI2SVKH
0.6
—
μs—
Hold time (repeated) START condition (after this period, the first
clock pulse is generated)
tI2SXKL
0.6
—
μs—
Data setup time
tI2DVKH
100
—
ns
—
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