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| 型號(hào)： | MPC8377EVRANGA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689 |
| 封裝： | 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689 |
| 文件頁(yè)數(shù)： | 32/124頁(yè) |
| 文件大?。?/td> | 1462K |
| 代理商： | MPC8377EVRANGA |
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
15
RESET Initialization
5.2
RESET AC Electrical Characteristics
Table 10 provides the reset initialization AC timing specifications of the device.
Table 11 provides the PLL lock times.
Table 10. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET to activate reset flow
32
—
tPCI_SYNC_IN
Required assertion time of PORESET with stable clock applied to CLKIN when
the device is in PCI host mode
32
—
tCLKIN
Required assertion time of PORESET with stable clock applied to PCI_CLK when
the device is in PCI agent mode
32
—
tPCI_SYNC_IN
HRESET assertion (output)
512
—
tPCI_SYNC_IN
HRESET negation to negation (output)
16
—
tPCI_SYNC_IN
Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],
CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET
when the device is in PCI host mode
4—
tCLKIN
2
Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],
CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET
when the device is in PCI agent mode
4—
tPCI_SYNC_IN
Input hold time for POR config signals with respect to negation of HRESET
0—
ns
—
Time for the device to turn off POR config signals with respect to the assertion of
HRESET
—4
ns
Time for the device to start driving functional output signals multiplexed with the
POR configuration signals with respect to the negation of HRESET
1—
tPCI_SYNC_IN
Note:
1 t
PCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary
clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the
MPC8379E
Integrated Host Processor Reference Manual for more details.
2 t
CLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode. See the
MPC8379E Integrated Host Processor Reference Manual for more details.
3 POR config signals consists of CFG_RESET_SOURCE[0:3], CFG_LBMUX, and CFG_CLKIN_DIV.
Table 11. PLL Lock Times
Parameter
Min
Max
Unit
Notes
PLL lock times
—
100
μs—
Note:
The device guarantees the PLL lock if the clock settings are within spec range. The core clock also depends on the core PLL
ratio. See Section 23, “Clocking,” for more information.
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