參數(shù)資料
型號(hào): MPC8360ECZUAGDGA
廠商: Freescale Semiconductor
文件頁數(shù): 6/102頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II PRO 740TBGA
標(biāo)準(zhǔn)包裝: 21
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 740-LBGA
供應(yīng)商設(shè)備封裝: 740-TBGA(37.5x37.5)
包裝: 托盤
配用: MPC8360EA-MDS-PB-ND - KIT APPLICATION DEV 8360 SYSTEM
MPC8360E-RDK-ND - BOARD REFERENCE DESIGN FOR MPC
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
11
Power Sequencing
This figure shows the undershoot and overshoot voltage of the PCI interface of the device for the 3.3-V signals, respectively.
Figure 4. Maximum AC Waveforms on PCI interface for 3.3-V Signaling
2.1.3
Output Driver Characteristics
This table provides information on the characteristics of the output driver strengths. The values are preliminary estimates.
2.2
Power Sequencing
This section details the power sequencing considerations for the MPC8360E/58E.
Table 3. Output Drive Capability
Driver Type
Output Impedance (
Ω)
Supply Voltage
Local bus interface utilities signals
42
OVDD = 3.3 V
PCI signals
25
PCI output clocks (including PCI_SYNC_OUT)
42
DDR signal
20
36 (half-strength mode)1
GVDD = 2.5 V
DDR2 signal
18
36 (half-strength mode)1
GVDD = 1.8 V
10/100/1000 Ethernet signals
42
LVDD = 2.5/3.3 V
DUART, system control, I2C, SPI, JTAG
42
OVDD = 3.3 V
GPIO signals
42
OVDD = 3.3 V
LVDD = 2.5/3.3 V
Note:
1. DDR output impedance values for half strength mode are verified by design and not tested.
Undervoltage
Waveform
Overvoltage
Waveform
11 ns
(Min)
+7.1 V
7.1 V p-to-p
(Min)
4 ns
(Max)
–3.5 V
7.1 V p-to-p
(Min)
62.5 ns
+3.6 V
0 V
4 ns
(Max)
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