參數(shù)資料
型號(hào): MPC8358CZQAGDGA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, RISC PROCESSOR, PBGA668
封裝: 29 X 29 MM, 1.46 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-668
文件頁(yè)數(shù): 75/95頁(yè)
文件大小: 1225K
代理商: MPC8358CZQAGDGA
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
Freescale Semiconductor
77
Clocking
The system VCO frequency is derived from the following equations:
csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
System VCO Frequency = csb_clk × VCO divider (if both RCWL[DDRCM] and RCWL[LBCM]
are cleared)
OR
System VCO frequency = 2
× csb_clk × VCO divider (if either RCWL[DDRCM] or
RCWL[LBCM] are set).
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 70
shows the expected frequency values for the CSB frequency for select csb_clk to CLKIN/PCI_SYNC_IN
ratios.
Table 70. CSB Frequency Options
CFG_CLKIN_DIV
at Reset1
SPMF
csb_clk:
Input Clock Ratio2
Input Clock Frequency (MHz)2
16.67
25
33.33
66.67
csb_clk Frequency (MHz)
Low
0010
2:1
133
Low
0011
3:1
100
200
Low
0100
4:1
100
133
266
Low
0101
5:1
125
166
333
Low
0110
6:1
100
150
200
Low
0111
7:1
116
175
233
Low
1000
8:1
133
200
266
Low
1001
9:1
150
225
300
Low
1010
10:1
166
250
333
Low
1011
11:1
183
275
Low
1100
12:1
200
300
Low
1101
13:1
216
325
Low
1110
14:1
233
Low
1111
15:1
250
Low
0000
16:1
266
High
0010
2:1
133
High
0011
3:1
100
200
High
0100
4:1
133
266
High
0101
5:1
166
333
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