參數(shù)資料
型號(hào): MPC8358CZQAGDGA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, RISC PROCESSOR, PBGA668
封裝: 29 X 29 MM, 1.46 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-668
文件頁(yè)數(shù): 64/95頁(yè)
文件大?。?/td> 1225K
代理商: MPC8358CZQAGDGA
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
Freescale Semiconductor
67
Package and Pin Listings
4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
5. Parallelism measurement must exclude any effect of mark on top surface of package.
6. Distance from the seating plane to the encapsulant material.
21.3
Pinout Listings
Refer to AN3097, “MPC8360/MPC8358E PowerQUICC Design Checklist,” for proper pin termination
and usage.
Table 65 shows the pin list of the MPC8358E PBGA package.
Table 65. MPC8358E PBGA Pinout Listing
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
DDR SDRAM Memory Controller Interface
MEMC_MDQ[0:63]
AD20, AG24, AF24, AH24, AF23, AE22, AH26, AD21,
AH25, AD22, AF27, AB24, AG25, AC22, AE25, AC24,
AD25, AB25, AC25, AG28, AD26, AE23, AG26, AC26,
AD27, V25, AA28, AA25, Y26, W27, U24, W24, E28,
H24, E26, D25, G27, H25, G26, F26, F27, F25, D26, F24,
G25, E27, D27, C28, C27, F22, B26, F21, B28, E22, D24,
C24, A25, E20, F20, D20, A23, C21, C23, E19
I/O
GVDD
MEMC_MECC[0:7]
N26, N24, J26, H28, N28, P24, L26, K24
I/O
GVDD
MEMC_MDM[0:8]
AG23, AD23, AE26, V28, G28, D28, D23, B24, U27
O
GVDD
MEMC_MDQS[0:8]
AH23, AH27, AF28, T28, H26, E25, B25, A24, R28
I/O
GVDD
MEMC_MBA[0:2]
V26, W28, Y28
O
GVDD
MEMC_MA[0:14]
L25, M25, M24, K28, P28, T24, M27, R25, P25, L28,
U26, M28, L27, K27, H27
OGVDD
MEMC_MODT[0:3]
AE21, AC19, E23, B23
GVDD
6
MEMC_MWE
R27
O
GVDD
MEMC_MRAS
W25
O
GVDD
MEMC_MCAS
R24
O
GVDD
MEMC_MCS[0:3]
T26, U28, J25, F28
O
GVDD
MEMC_MCKE[0:1]
AD24, AE28
O
GVDD
MEMC_MCK[0:5]
AG22, AG27, A26, C26, P26, E21
O
GVDD
MEMC_MCK[0:5]
AF22, AF26, A27, B27, N27, D22
O
GVDD
MDIC[0:1]
F19, AA27
I/O
GVDD
11
PCI
PCI_INTA/
PF[5]
R3
I/O
LVDD22
PCI_RESET_OUT/
PF[6]
P6
I/O
LVDD2—
PCI_AD[0:31]/
PG[0:31]
AB5, AC5, AG1, AA5, AF2, AD4, Y6, AF1, AE2, AC4,
AD3, AE1, Y4, AC3, AD2, AD1, AB2, Y3, AA1, Y1, W1,
V6, W3, V4, T5, W2, V5, V1, U4, V2, U2, T2
I/O
LVDD2—
PCI_C_BE[0:3]/
PF[7:10]
Y5, AC2, Y2, U5
I/O
OVDD
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