參數(shù)資料
型號(hào)： MPC8349ZUAJD
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 533 MHz, RISC PROCESSOR, PBGA672
封裝： 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-672
文件頁(yè)數(shù)： 15/108頁(yè)
文件大?。?/td> 1275K
代理商： MPC8349ZUAJD
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 7
14
Freescale Semiconductor
Clock Input Timing
4
Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8349E.
4.1
DC Electrical Characteristics
Table 7 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8349E.
4.2
AC Electrical Characteristics
The primary clock source for the MPC8349E can be one of two inputs, CLKIN or PCI_CLK, depending
on whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock input
(CLKIN/PCI_CLK) AC timing specifications for the MPC8349E.
Table 6. CLKIN DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
Input high voltage
—
VIH
2.7
OVDD+0.3
V
Input low voltage
—
VIL
–0.3
0.4
V
CLKIN Input current
0V
≤V
IN ≤ OVDD
IIN
—
±10
μA
PCI_SYNC_IN Input current
0V
≤V
IN ≤ 0.5 V or
OVDD – 0.5 V
≤V
IN ≤ OVDD
IIN
—
±10
μA
PCI_SYNC_IN Input current
0.5 V
≤V
IN ≤ OVDD - 0.5 V
IIN
—
±50
μA
Table 7. CLKIN AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
CLKIN/PCI_CLK frequency
fCLKIN
——
66
MHz
1
CLKIN/PCI_CLK cycle time
tCLKIN
15
—
ns
—
CLKIN/PCI_CLK rise and fall time
tKH, tKL
0.6
1.0
2.3
ns
2
CLKIN/PCI_CLK duty cycle
tKHK/tCLKIN
40
—
60
%
3
CLKIN/PCI_CLK jitter
—
+/– 150
ps
4, 5
Notes:
1. Caution: The system, core, USB, security, and TSEC must not exceed their respective maximum or minimum
operating frequencies.
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set
low to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
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