參數(shù)資料
型號(hào)： MPC8349CZUAGF
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA672
封裝： 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-672
文件頁(yè)數(shù)： 6/88頁(yè)
文件大?。?/td> 1014K
代理商： MPC8349CZUAGF
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
14
Freescale Semiconductor
RESET Initialization
Table 10 lists the PLL and DLL lock times.
Input hold time for POR configuration signals with respect to
negation of HRESET
0—
ns
Time for the MPC8349E to turn off POR configuration signals
with respect to the assertion of HRESET
—4
ns
3
Time for the MPC8349E to turn on POR configuration signals
with respect to the negation of HRESET
1—
tPCI_SYNC_IN
1, 3
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied
to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the
MPC8349E
PowerQUICC II Pro Integrated Host Processor Family Reference Manual.
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349E
PowerQUICC II Pro Integrated Host Processor Family Reference Manual.
3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Table 10. PLL and DLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
—
100
μs
DLL lock times
7680
122,880
csb_clk cycles
1, 2
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
results in the minimum and an 8:1 ratio results in the maximum.
2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 19, “Clocking.”
Table 9. RESET Initialization Timing Specifications (continued)
Parameter/Condition
Min
Max
Unit
Notes
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