參數(shù)資料
型號(hào): MPC8349CZUAGF
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA672
封裝: 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-672
文件頁(yè)數(shù): 12/88頁(yè)
文件大?。?/td> 1014K
代理商: MPC8349CZUAGF
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
2
Freescale Semiconductor
Overview
1Overview
This section provides a high-level overview of the MPC8349E features. Figure 1 shows the major
functional units within the MPC8349E.
Figure 1. MPC8349E Block Diagram
Major features of the MPC8349E are as follows:
Embedded PowerPC e300 processor core; operates at up to 667 MHz
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the other Freescale processor families that implement Power
Architecture technology
Double data rate, DDR SDRAM memory controller
— Programmable timing for DDR-1 SDRAM
— 32- or 64-bit data interface, up to 333-MHz data rate
— Four banks of memory, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbit to 1 Gbit with x8/x16 data ports
— Full error checking and correction (ECC) support
— Page mode support (up to 16 simultaneous open pages)
TSEC
Coherent System Bus
PCI1
10/100/1Gb
MII, GMII, TBI,
RTBI, RGMII
SPI
Serial
IRQs
ROM
I2C
I2C Interfaces
TSEC
DDR
Memory Controller
Local Bus Controller
Programmable Interrupt
Controller
DUART
e300 Core
DMA Controller
Serial Peripheral
Interface
32-Kbyte L1
Instruction
Cache
32-Kbyte
L1 Data
Cache
Sequencer
SEQ
64/32b PCI Controller
PCI2
0/32b PCI Controller
Security Engine
Arbiter Bus
Monitor
USB Hi-Speed
Host Device
General Purpose I/O
USB0
USB1
GPIO
SDRAM
DDR
SDRAM
DMA
MII, GMII, TBI,
RTBI, RGMII
10/100/1Gb
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