參數(shù)資料
型號(hào)： MPC8349CZUAGF
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA672
封裝： 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-672
文件頁(yè)數(shù)： 28/88頁(yè)
文件大?。?/td> 1014K
代理商： MPC8349CZUAGF
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
34
Freescale Semiconductor
Local Bus
10 Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the
MPC8349E.
10.1
Local Bus DC Electrical Characteristics
Table 33 provides the DC electrical characteristics for the local bus interface.
10.2
Local Bus AC Electrical Specification
Table 34 and Table 35 describe the general timing parameters of the local bus interface of the MPC8349E.
Table 33. Local Bus DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2OVDD +0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
Input current
IIN
—±5
μA
High-level output voltage, IOH = –100 μAVOH
OVDD –0.2
—
V
Low-level output voltage, IOL = 100 μAVOL
—0.2
V
Table 34. Local Bus General Timing Parameters—DLL On
Parameter
Symbol1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
7.5
—
ns
2
Input setup to local bus clock (except LUPWAIT)
tLBIVKH1
1.5
—
ns
3, 4
LUPWAIT input setup to local bus clock
tLBIVKH2
2.2
—
ns
3, 4
Input hold from local bus clock (except LUPWAIT)
tLBIXKH1
1.0
—
ns
3, 4
LUPWAIT Input hold from local bus clock
tLBIXKH2
1.0
—
ns
3, 4
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT1
1.5
—
ns
5
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT2
3—
ns
6
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT3
2.5
—
ns
7
Local bus clock to LALE rise
tLBKHLR
—4.5
ns
Local bus clock to output valid (except LAD/LDP and LALE)
tLBKHOV1
—4.5
ns
Local bus clock to data valid for LAD/LDP
tLBKHOV2
—4.5
ns
3
Local bus clock to address valid for LAD
tLBKHOV3
—4.5
ns
3
Output hold from local bus clock (except LAD/LDP and LALE)
tLBKHOX1
1—
ns
3
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