參數(shù)資料
型號： MPC8349CVVAGD
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, RISC PROCESSOR, PBGA672
封裝： 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-672
文件頁數(shù)： 36/108頁
文件大?。?/td> 1275K
代理商： MPC8349CVVAGD
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
33
Ethernet: Three-Speed Ethernet, MII Management
8.2.2.2
MII Receive AC Timing Specifications
Table 24 provides the MII receive AC timing specifications.
Figure 10 provides the AC test load for TSEC.
Figure 10. TSEC AC Test Load
Figure 11 shows the MII receive AC timing diagram.
Figure 11. MII Receive AC Timing Diagram
Table 24. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V ± 10%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
tMRX
—400
—
ns
RX_CLK clock period 100 Mbps
tMRX
—40—
ns
RX_CLK duty cycle
tMRXH/tMRX
35
—
65
%
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
—
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
—
ns
RX_CLK clock rise VIL(min) to VIH(max)
tMRXR
1.0
—
4.0
ns
RX_CLK clock fall time VIH(max) to VIL(min)
tMRXF
1.0
—
4.0
ns
Note:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing
(MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to
the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals
(D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. In general, the clock
reference symbol is based on three letters representing the clock of a particular functionl. For example, the subscript of tMRX
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R
(rise) or F (fall).
Output
Z0 = 50 Ω
LVDD/2
RL = 50 Ω
RX_CLK
RXD[3:0]
tMRDXKH
tMRX
tMRXH
tMRXR
tMRXF
RX_DV
RX_ER
tMRDVKH
Valid Data
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參數(shù)描述
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MPC8349CVVAGFB 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications
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MPC8349CVVALDB 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications
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