參數(shù)資料
型號(hào): MPC8349CVVAGD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, RISC PROCESSOR, PBGA672
封裝: 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-672
文件頁(yè)數(shù): 23/108頁(yè)
文件大?。?/td> 1275K
代理商: MPC8349CVVAGD
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
21
DDR SDRAM
6.2.2
DDR SDRAM Output AC Timing Specifications
Table 14 and Table 15 provide the output AC timing specifications and measurement conditions for the
DDR SDRAM interface.
Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter
Symbol 1
Min
Max
Unit
Notes
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
tMCK
610
ns
2
Skew between any MCK to ADDR/CMD
333 MHz
266 MHz
200 MHz
tAOSKEW
-1000
-1100
-1200
200
300
400
ps
3
ADDR/CMD output setup with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHAS
2.8
3.45
4.6
—ns
4
ADDR/CMD output hold with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHAX
2.0
2.65
3.8
—ns
4
MCS(n) output setup with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHCS
2.8
3.45
4.6
—ns
4
MCS(n) output hold with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHCX
2.0
2.65
3.8
—ns
4
MCK to MDQS
333 MHz
266 MHz
200 MHz
tDDKHMH
-0.9
-1.1
-1.2
0.3
0.5
0.6
ns
5
MDQ/MECC/MDM output setup with respect to
MDQS
333 MHz
266 MHz
200 MHz
tDDKHDS,
tDDKLDS
900
1200
—ps
6
MDQ/MECC/MDM output hold with respect to
MDQS
333 MHz
266 MHz
200 MHz
tDDKHDX,
tDDKLDX
900
1200
—ps
6
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