參數(shù)資料
型號(hào): MPC8323EZQAFDC
廠(chǎng)商: Freescale Semiconductor
文件頁(yè)數(shù): 30/82頁(yè)
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II 516-PBGA
產(chǎn)品培訓(xùn)模塊: MPC8323E PowerQUICC II Pro Processor
標(biāo)準(zhǔn)包裝: 40
系列: MPC83xx
處理器類(lèi)型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
電壓: 1V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 516-BBGA
供應(yīng)商設(shè)備封裝: 516-FPBGA(27x27)
包裝: 托盤(pán)
配用: MPC8323E-RDB-ND - BOARD REFERENCE DESIGN
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
36
Freescale Semiconductor
PCI
Table 37 shows the PCI AC timing specifications at 33 MHz.
Figure 25 provides the AC test load for PCI.
Figure 25. PCI AC Test Load
Figure 26 shows the PCI input AC timing conditions.
Figure 26. PCI Input AC Timing Measurement Conditions
Table 37. PCI AC Timing Specifications at 33 MHz
Parameter
Symbol1
Min
Max
Unit
Notes
Clock to output valid
tPCKHOV
—11
ns
2
Output hold from clock
tPCKHOX
2—
ns
2
Clock to output high impedence
tPCKHOZ
—14
ns
2, 3
Input setup to clock
tPCIVKH
3.0
ns
2, 4
Input hold from clock
tPCIXKH
0—
ns
2, 4
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing
(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference
(K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset
(R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the
PCI 2.3 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
tPCIVKH
CLK
Input
tPCIXKH
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