參數(shù)資料
型號(hào): MPC8323EZQAFDC
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 19/82頁(yè)
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II 516-PBGA
產(chǎn)品培訓(xùn)模塊: MPC8323E PowerQUICC II Pro Processor
標(biāo)準(zhǔn)包裝: 40
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 516-BBGA
供應(yīng)商設(shè)備封裝: 516-FPBGA(27x27)
包裝: 托盤
配用: MPC8323E-RDB-ND - BOARD REFERENCE DESIGN
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
26
Freescale Semiconductor
Local Bus
Figure 13 shows the MII management AC timing diagram.
Figure 13. MII Management Interface Timing Diagram
9
Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the
MPC8323E.
9.1
Local Bus DC Electrical Characteristics
Table 29 provides the DC electrical characteristics for the local bus interface.
9.2
Local Bus AC Electrical Specifications
Table 30 describes the general timing parameters of the local bus interface of the MPC8323E.
Table 29. Local Bus DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2OVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
High-level output voltage, IOH = –100 μAVOH
OVDD – 0.2
V
Low-level output voltage, IOL = 100 μAVOL
—0.2
V
Input current
IIN
—±5
μA
Table 30. Local Bus General Timing Parameters
Parameter
Symbol1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
15
ns
2
Input setup to local bus clock (LCLK
n)tLBIVKH
7—
ns
3, 4
Input hold from local bus clock (LCLK
n)tLBIXKH
1.0
ns
3, 4
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT1
1.5
ns
5
MDC
tMDDXKH
tMDC
tMDCH
tMDCR
tMDCF
tMDDVKH
tMDKHDX
MDIO
(Input)
(Output)
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