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| 型號： | MPC8315VRAGDA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 74/106頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC II PRO 620-PBGA |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 400MHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 620-BBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 620-PBGA（29x29） |
| 包裝： | 托盤 |
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MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
7
MPC8315E Features
2.12
Power Management Controller (PMC)
The MPC8315E supports a range of power management states that significantly lower power consumption
under the control of the power management controller. The PMC includes the following features:
Provides power management when the device is used in both PCI host and agent modes
PCI Power Management 1.2 D0, D1, D2, D3hot, and D3cold states
PME generation in PCI agent mode, PME detection in PCI host mode
Wake-up from Ethernet (magic packet), USB, GPIO, and PCI (PME input as host) while in the D1,
D2 and D3hot states
A new low-power standby power management state called D3warm
— The PMC, one Ethernet port, and the GTM block remain powered via a split power supply
controlled through an external power switch
— Wake-up events include Ethernet (magic packet), GTM, GPIO, or IRQ inputs and cause the
device to transition back to normal operation
— PCI agent mode is not be supported in D3warm state
PCI Express-based PME events are not supported
2.13
Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) allows the MPC8315E to exchange data between other PowerQUICC
family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time
clocks, A/D converters, and ISDN devices.
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface
(receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an
independent baud-rate generator, and a control unit.
2.14
DMA Controller, I2C, DUART, Enhanced Local Bus Controller
(eLBC), and Timers
The integrated four-channel DMA controller includes the following features:
Allows chaining (both extended and direct) through local memory-mapped chain descriptors
(accessible by local masters)
Misaligned transfer capability for source/destination address
Supports external DREQ, DACK and DONE signals
There is one I2C controller. This synchronous, multi-master buses can be connected to additional devices
for expansion and system development.
The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550
programming models. 16-byte FIFOs are supported for both the transmitter and the receiver.
The eLBC port allows connections with a wide variety of external DSPs and ASICs. Three separate state
machines share the same external pins and can be programmed separately to access different types of
devices. The general-purpose chip select machine (GPCM) controls accesses to asynchronous devices
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