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| 型號： | MPC8315VRAGDA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 70/106頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC II PRO 620-PBGA |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 400MHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 620-BBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 620-PBGA（29x29） |
| 包裝： | 托盤 |
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MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
66
Freescale Semiconductor
PCI Express
Powered down DC input
impedance
ZRX-HIGH-IMP-DC
Required RX D+ as well as D-
DC Impedance when the
Receiver terminations do not
have power.
200 k
—
6
Electrical idle detect
threshold
VRX-IDLE-DET-DIFFp-p
VPEEIDT = 2*|VRX-D+ -VRX-D-|
Measured at the package pins of
the Receiver
65
—
175
mV
—
Unexpected Electrical Idle
Enter Detect Threshold
Integration Time
TRX-IDLE-DET-DIFF-
ENTERTIME
An unexpected Electrical Idle
(Vrx-diffp-p <
Vrx-idle-det-diffp-p) must be
recognized no longer than
Trx-idle-det-diff-entertime to
signal an unexpected idle
condition.
——
10
ms
—
Total Skew
LRX-SKEW
Skew across all lanes on a Link.
This includes variation in the
length of SKP ordered set (e.g.
COM and one to five SKP
Symbols) at the RX as well as
any delay differences arising
from the interconnect itself.
—
20
ns
—
Note:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 52 should be used as the
RX device when taking measurements (also refer to the receiver compliance eye diagram shown in Figure 51). If the clocks to the
RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as a
reference for the eye diagram.
3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect
collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median
and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any 250 consecutive TX UIs.
It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of
jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not
derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as the reference for the eye
diagram.
4. The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to 300
mV and the D– line biased to –300 mV and a common mode return loss greater than or equal to 6 dB (no bias required) over a
frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference
impedance for return loss measurements for is 50
to ground for both the D+ and D– line (that is, as measured by a vector network
analyzer with 50-
probes, see Figure 52). Note that the series capacitors, C
TX, is optional for the return loss measurement.
5. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there is
a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
6. The RX DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure
that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300
mV above the RX ground.
7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm
using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated data.
Table 55. Differential Receiver (RX) Input Specifications (continued)
Parameter
Symbol
Comments
Min
Typical
Max
Unit
Note
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