參數(shù)資料
型號： MPC8315VRAGDA
廠商： Freescale Semiconductor
文件頁數(shù)： 41/106頁
文件大?。?/td> 0K
描述： MPU POWERQUICC II PRO 620-PBGA
標(biāo)準(zhǔn)包裝： 36
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 620-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 620-PBGA（29x29）
包裝： 托盤
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
4
Freescale Semiconductor
MPC8315E Features
— Combines a True Random Number Generator (TRNG) and a NIST-approved Pseudo-Random
Number Generator (PRNG) (as described in Annex C of FIPS140-2 and ANSI X9.62).
Cyclical Redundancy Check Hardware Accelerator (CRCA)
— Implements CRC32C as required for iSCSI header and payload checksums, CRC32 as required
for IEEE 802 packets, as well as for programmable 32 bit CRC polynomials
2.4
DDR Memory Controller
The DDR1/DDR2 memory controller includes the following features:
Single 16- or 32-bit interface supporting both DDR1 and DDR2 SDRAM
Support for up to 266 MHz data rate
Support for two physical banks (chip selects), each bank independently addressable
64-Mbit to 2-Gbit (for DDR1) and to 4-Gbit (for DDR2) devices with x8/x16 data ports (no direct
x4 support)
Support for one 16-bit device or two 8-bit devices on a 16-bit bus or two 16-bit devices on a 32-bit
bus
Support for up to 16 simultaneous open pages
Supports auto refresh
On-the-fly power management using CKE
1.8-/2.5-V SSTL2 compatible I/O
2.5
PCI Controller
The PCI controller includes the following features:
Designed to comply with PCI Local Bus Specification Revision 2.3
Single 32-bit data PCI interface operates at up to 66 MHz
PCI 3.3-V compatible (not 5-V compatible)
Support for host and agent modes
On-chip arbitration, supporting three external masters on PCI
Selectable hardware-enforced coherency
2.6
TDM Interface
The TDM interface includes the following features:
Independent receive and transmit with dedicated data, clock and frame sync line
Separate or shared RCK and TCK whose source can be either internal or external
Glueless interface to E1/T1 frames and MVIP, SCAS, and H.110 buses
Up to 128 time slots, where each slot can be programmed to be active or inactive
8- or 16-bit word widths
The TDM Transmitter Sync Signal (TFS), Transmitter Clock Signal (TCK) and Receiver Clock
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