參數(shù)資料
型號(hào): MPC8313EVRADDB
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 47/99頁(yè)
文件大小: 0K
描述: MPU POWERQUICC II PRO 516-PBGA
標(biāo)準(zhǔn)包裝: 40
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 267MHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 516-BBGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 516-PBGAPGE(27x27)
包裝: 托盤(pán)
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
51
12 JTAG
This section describes the DC and AC electrical specifications for the IEEE Std 1149.1 (JTAG)
interface.
12.1
JTAG DC Electrical Characteristics
This table provides the DC electrical characteristics for the IEEE Std 1149.1 (JTAG) interface.
12.2
JTAG AC Timing Specifications
This section describes the AC electrical specifications for the IEEE Std 1149.1 (JTAG) interface. This table
provides the JTAG AC timing specifications as defined in Figure 41 through Figure 45.
Table 46. JTAG Interface DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—2.1
NVDD +0.3
V
Input low voltage
VIL
—–0.3
0.8
V
Input current
IIN
——
±5
A
Output high voltage
VOH
IOH = –8.0 mA
2.4
V
Output low voltage
VOL
IOL = 8.0 mA
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
0.4
V
Table 47. JTAG AC Timing Specifications (Independent of SYS_CLK_IN)1
At recommended operating conditions (see Table 2).
Parameter
Symbol2
Min
Max
Unit
Note
JTAG external clock frequency of operation
fJTG
033.3
MHz
JTAG external clock cycle time
t JTG
30
ns
JTAG external clock pulse width measured at 1.4 V
tJTKHKL
15
ns
JTAG external clock rise and fall times
tJTGR & tJTGF
02
ns
TRST assert time
tTRST
25
ns
3
Input setup times:
Boundary-scan data
TMS, TDI
tJTDVKH
tJTIVKH
4
ns
4
Input hold times:
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
10
ns
4
Valid times:
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
2
11
ns
5
Output hold times:
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
2
ns
5
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