參數(shù)資料
型號(hào)： MPC8313ECVRAGDB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 96/99頁(yè)
文件大?。?/td> 0K
描述： MPU POWERQUICC II PRO 516-PBGA
標(biāo)準(zhǔn)包裝： 40
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 516-PBGAPGE（27x27）
包裝： 托盤
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
96
Freescale Semiconductor
2
10/2008
Added Note “The information in this document is accurate for revision 1.0, and 2.x and later. See
Section 24.1, “Part Numbers Fully Addressed by this Document,” before Section 1, “Overview.”
Added part numbering details for all the silicon revisions in Table 74.
Changed VIH from 2.7 V to 2.4 V in Table 7.
Added a row for VIH level for Rev 2.x or later in Table 45.
Added a column for maximum power dissipation in low power mode for Rev 2.x or later silicon in
Table 6.
Added a column for Power Nos for Rev 2.x or later silicon and added a row for 400 MHz in Table 4.
Removed footnote, “These are preliminary estimates.” from Table 4.
Added Table 21 for DDR AC Specs on Rev 2.x or later silicon.
Added Section 9, “High-Speed Serial Interfaces (HSSI).”
Added LFWE, LFCLE, LFALE, LOE, LFRE, LFWP, LGTA, LUPWAIT, and LFRB in Table 63.
In Table 39, added note 2: “This parameter is dependent on the csb_clk speed. (The MIIMCFG[Mgmt
Clock Select] field determines the clock frequency of the Mgmt Clock EC_MDC.)”
Removed mentions of SGMII (SGMII has separate specs) from Section 8.1, “Enhanced Three-Speed
Ethernet Controller (eTSEC) (10/100/1000 Mbps)—MII/RMII/RGMII/SGMII/RTBI Electrical
Characteristics.”
Corrected Section 8.1, “Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1000 Mbps)—MII/RMII/RGMII/SGMII/RTBI Electrical Characteristics,” to state that
RGMII/RTBI interfaces only operate at 2.5 V, not 3.3 V.
Added ZQ package to ordering information In Table 74 and Section 19.1, “Package Parameters for the
MPC8313E TEPBGAII” (applicable to both silicon rev. 1.0 and 2.1)
Removed footnotes 5 and 6 from Table 1 (left over when the PCI undershoot/overshoot voltages and
maximum AC waveforms were removed from Section 2.1.2, “Power Supply Voltage Specification”).
Removed SD_PLL_TPD (T2) and SD_PLL_TPA_ANA (R4) from Table 63.
Added Section 8.3, “SGMII Interface Electrical Characteristics.” Removed Section 8.5.3 SGMII DC
Electrical Characteristics.
Removed “HRESET negation to SRESET negation (output)” spec and changed “HRESET/SRESET
assertion (output)” spec to “HRESET assertion (output)” in Table 10.
Clarified POR configuration signal specs to “Time for the device to turn off POR configuration signal
drivers with respect to the assertion of HRESET” and “Time for the device to turn on POR configuration
signal drivers with respect to the negation of HRESET” in Table 10.
Added Section 24.2, “Part Marking,” and Figure 62.
Table 73. Document Revision History (continued)
Rev.
Number
Date
Substantive Change(s)
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