參數(shù)資料
型號： MPC8313ECVRAGDB
廠商： Freescale Semiconductor
文件頁數(shù)： 31/99頁
文件大?。?/td> 0K
描述： MPU POWERQUICC II PRO 516-PBGA
標準包裝： 40
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA 裸露焊盤
供應商設備封裝： 516-PBGAPGE（27x27）
包裝： 托盤
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
37
The common mode voltage is equal to one half of the sum of the voltages between each conductor
of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out =
(VTXn +VTXn)/2 = (A + B)/2, which is the arithmetic mean of the two complimentary output
voltages within a differential pair. In a system, the common mode voltage may often differ from
one component’s output to the other’s input. Sometimes, it may be even different between the
receiver input and driver output circuits within the same component. It’s also referred as the DC
offset in some occasion.
Figure 22. Differential Voltage Definitions for Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (current mode logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD or
TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since the
differential signaling environment is fully symmetrical, the transmitter output’s differential swing (VOD)
has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between
500 and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak
differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.
9.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks input is SD_REF_CLK and SD_REF_CLK
for SGMII interface.
The following sections describe the SerDes reference clock requirements and some application
information.
9.2.1
SerDes Reference Clock Receiver Characteristics
Figure 23 shows a receiver reference diagram of the SerDes reference clocks.
The supply voltage requirements for XCOREVDD are specified in Table 1 and Table 2.
SerDes reference clock receiver reference circuit structure:
A Volts
B Volts
TXn or RXn
Vcm = (A + B)/2
Differential Swing, VID or VOD = A – B
Differential Peak Voltage, VDIFFp = |A – B|
Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown)
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相關代理商/技術參數(shù)
參數(shù)描述
MPC8313ECVRAGDC 功能描述:微處理器 - MPU 8313 REV2.2 W/ENC EXT RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8313ECVRGDD 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications
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MPC8313ECVRGDDB 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications
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