參數(shù)資料
型號(hào): MPC8313ECVRAGDB
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 4/99頁(yè)
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 516-PBGA
標(biāo)準(zhǔn)包裝: 40
系列: MPC83xx
處理器類(lèi)型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 0.95 V ~ 1.05 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 516-BBGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 516-PBGAPGE(27x27)
包裝: 托盤(pán)
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
12
Freescale Semiconductor
This table shows the estimated core power dissipation of the MPC8313E while transitioning into the
D3 warm low-power state.
4
Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8313E.
4.1
DC Electrical Characteristics
This table provides the system clock input (SYS_CLK_IN/PCI_SYNC_IN) DC timing specifications for
the MPC8313E.
USBDR controller load = 20 pF
60 MHz
0.078
W
Other I/O
0.015
W
Table 6. MPC8313E Low-Power Modes Power Dissipation1
333-MHz Core, 167-MHz CSB
2
Rev. 1.0
3
Rev. 2.x or Later
3
Unit
D3 warm
400
425
mW
Note:
1. All interfaces are enabled. For further power savings, disable the clocks to unused blocks.
2. The interfaces are run at the following frequencies: DDR: 333 MHz, eLBC 83 MHz, PCI 33 MHz,
eTSEC1 and TSEC2: 167 MHz, SEC: 167 MHz, USB: 167 MHz. See the SCCR register for more
information.
3. This is maximum power in D3 Warm based on a voltage of 1.05 V and a junction temperature of 105
C.
Table 7. SYS_CLK_IN DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
Input high voltage
VIH
2.4
NVDD +0.3
V
Input low voltage
VIL
–0.3
0.4
V
SYS_CLK_IN input current
0 V
V
IN NVDD
IIN
—±10
A
PCI_SYNC_IN input current
0 V
V
IN 0.5 V
or
NVDD – 0.5 V VIN NVDD
IIN
—±10
A
PCI_SYNC_IN input current
0.5 V
V
IN NVDD –0.5V
IIN
±50
A
Table 5. MPC8313E Typical I/O Power Dissipation (continued)
Interface
Parameter
GVDD
(1.8 V)
GVDD
(2.5 V)
NVDD
(3.3 V)
LVDDA/
LVDDB
(3.3 V)
LVDDA/
LVDDB
(2.5 V)
LVDD
(3.3 V)
Unit
Comments
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