參數(shù)資料
型號(hào)： MPC8306VMABDCA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 133 MHz, RISC PROCESSOR, PBGA369
封裝： 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-369
文件頁(yè)數(shù)： 11/76頁(yè)
文件大?。?/td> 474K
代理商： MPC8306VMABDCA
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
19
Local Bus
7
Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the MPC8306.
7.1
Local Bus DC Electrical Characteristics
Table 17 provides the DC electrical characteristics for the local bus interface.
7.2
Local Bus AC Electrical Specifications
Table 18 describes the general timing parameters of the local bus interface of the MPC8306.
Table 17. Local Bus DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2OVDD +0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
High-level output voltage, IOH = –100 AVOH
OVDD –0.2
—
V
Low-level output voltage, IOL =100 AVOL
—0.2
V
Input current
IIN
—±5
A
Table 18. Local Bus General Timing Parameters
Parameter
Symbol1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
15
—
ns
2
Input setup to local bus clock (LCLKn)tLBIVKH
7
—
ns
3, 4
Input hold from local bus clock (LCLKn)tLBIXKH
1.0
—
ns
3, 4
Local bus clock (LCLKn) to output valid
tLBKHOV
—3
ns
3
Local bus clock (LCLKn) to output high impedance for LAD/LDP
tLBKHOZ
—4
ns
5
Notes
:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case
for clock one(1).
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4 OVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
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