參數(shù)資料
型號(hào)： MPC8306CVMACDCA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA369
封裝： 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-369
文件頁(yè)數(shù)： 59/76頁(yè)
文件大?。?/td> 474K
代理商： MPC8306CVMACDCA
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
62
Freescale Semiconductor
Clocking
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset.
Table 53 specifies which units have a configurable clock frequency. For detailed description, refer to the
“System Clock Control Register (SCCR)” section in the MPC8306 PowerQUICC II Pro Communications
Processor Reference Manual.
NOTE
Setting the clock ratio of these units must be performed prior to any access
to them.
Table 54 provides the maximum operating frequencies for the MPC8306 MAPBGA under recommended
operating conditions (see Table 2).
22.2
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 55 shows the multiplication factor
encodings for the system PLL.
NOTE
System PLL VCO frequency = 2 × (CSB frequency) × (System PLL VCO
divider). The VCO divider needs to be set properly so that the System PLL
VCO frequency is in the range of 450–750 MHz.
As described in Section 22, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset
configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal
Table 53. Configurable Clock Units
Unit
Default Frequency
Options
I2C,SDHC, USB, DMA Complex
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
Table 54. Operating Frequencies for MAPBGA
Characteristic1
1 The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk,
MCLK, LCLK, and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
Max Operating Frequency
Unit
e300 core frequency (core_clk)266
MHz
Coherent system bus frequency (csb_clk)133
MHz
QUICC Engine frequency (qe_clk)200
MHz
DDR2 memory bus frequency (MCLK)2
2 The DDR2 data rate is 2× the DDR2 memory bus frequency.
133
MHz
Local bus frequency (LCLKn)3
3 The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1× or 2× the
csb_clk
frequency (depending on RCWL[LBCM]).
66
MHz
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參數(shù)描述
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MPC8306EC 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications
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