參數(shù)資料
型號(hào)： MPC8306CVMACDCA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA369
封裝： 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-369
文件頁(yè)數(shù)： 35/76頁(yè)
文件大?。?/td> 474K
代理商： MPC8306CVMACDCA
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
40
Freescale Semiconductor
I2C
15 I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8306.
15.1
I2C DC Electrical Characteristics
Table 40 provides the DC electrical characteristics for the I2C interface of the MPC8306.
15.2
I2C AC Electrical Specifications
Table 41 provides the AC timing parameters for the I2C interface of the MPC8306.
Table 40. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 300mV.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage level
VIH
0.7
OVDD
OVDD +0.3
V
—
Input low voltage level
VIL
–0.3
0.3
OVDD
V—
Low level output voltage
VOL
00.4
V
1
Output fall time from VIH(min) to VIL(max) with a bus
capacitance from 10 to 400 pF
tI2KLKV
20 + 0.1
CB
250
ns
2
Pulse width of spikes which must be suppressed by the
input filter
tI2KHKL
050
ns
3
Capacitance for each I/O pin
CI
—10
pF
—
Input current (0 V
VIN OVDD)IIN
—±5
A4
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the
MPC8306 PowerQUICC II Pro Integrated Communications Processor Reference Manual for information on
the digital filter used.
4. I/O pins obstructs the SDA and SCL lines if OVDD is switched off.
Table 41. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 40).
Parameter
Symbol1
Min
Max
Unit
SCL clock frequency
fI2C
0
400
kHz
Low period of the SCL clock
tI2CL
1.3
—
s
High period of the SCL clock
tI2CH
0.6
—
s
Setup time for a repeated START condition
tI2SVKH
0.6
—
s
Hold time (repeated) START condition (after this period, the first clock
pulse is generated)
tI2SXKL
0.6
—
s
Data setup time
tI2DVKH
100
—
ns
Data hold time: I2C bus devices
tI2DXKL
300
0.93
s
Rise time of both SDA and SCL signals
tI2CR
20 + 0.1 CB4
300
ns
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