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參數(shù)資料
| 型號： | MPC8275VR |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerQUICC II Family Hardware Specifications |
| 中文描述： | 的PowerQUICC II系列硬件規(guī)格 |
| 文件頁數(shù)： | 4/76頁 |
| 文件大?。?/td> | 496K |
| 代理商： | MPC8275VR |
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MPC8280 PowerQUICC II Family Hardware Specifications
MOTOROLA
Overview
— High-performance (SPEC95 benchmark at 450 MHz; 855 Dhrystones MIPS at 450 MHz)
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
Separate power supply for internal logic and for I/O
Separate PLLs for G2_LE core and for the CPM
— G2_LE core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 6:1, 7:1,
8:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1 ratios
64-bit data and 32-bit address 60x bus
— Bus supports multiple master designs
— Supports single- and four-beat burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
32-bit data and 18-bit address local bus
— Single-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge
— Programmable host bridge and agent
— 32-bit data bus, 66.67/83.3/100 MHz, 3.3 V
— Synchronous and asynchronous 60x and PCI clock modes
— All internal address space available to external PCI host
— DMA for memory block transfers
— PCI-to-60x address remapping
PCI bridge
— PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz
— On-chip arbitration
— Support for PCI-to-60x-memory and 60x-memory-to-PCI streaming
— PCI host bridge or periphera
l
capabilities
— Includes 4 DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI
— Includes all of the configuration registers (which are automatically loaded from the EPROM
and used to configure the MPC8280) required by the PCI standard as well as message and
doorbell registers
— Supports the I
2
O standard
— Hot-swap friendly (supports the hot swap specification as defined by PICMG 2.1 R1.0 August
3, 1998)
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| MPC850DE | Communications Controller Hardware Specifications |
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| MPC850ED | Communications Controller Hardware Specifications |
| MPC850SAR | Communications Controller Hardware Specifications |
| MPC859P | PowerQUICC⑩ Family Technical Summary |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8275VRB | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8275VRE | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8275VRI | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8275VRM | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8275VRMIBA | 功能描述:微處理器 - MPU 266 MHz 505.4 MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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