參數(shù)資料
型號(hào): MPC8275VR
廠商: Motorola, Inc.
英文描述: PowerQUICC II Family Hardware Specifications
中文描述: 的PowerQUICC II系列硬件規(guī)格
文件頁(yè)數(shù): 14/76頁(yè)
文件大?。?/td> 496K
代理商: MPC8275VR
14
MPC8280 PowerQUICC II Family Hardware Specifications
MOTOROLA
Power Dissipation
5
Power Dissipation
Table 7 provides preliminary, estimated power dissipation for various configurations. Note that suitable
thermal management is required to ensure the junction temperature does not exceed the maximum specified
value. Also note that the I/O power should be included when determining whether to use a heat sink. For a
complete list of possible clock configurations, refer to Section 7, “Clock Configuration Modes.”
Table 7. Estimated Power Dissipation for Various Configurations
1
6
The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and
inputs for 66.67/83.33/100 MHz devices. Note that AC timings are based on a 50-p
f
load. Typical output
buffer impedances are shown in Table 8.
Table 8. Output Buffer Impedances
1
AC Electrical Characteristics
1
Test temperature = 105
C
2
P
INT
= I
DD
x V
DD
Watts
3
Values do not include I/O. Add the following estimates for active I/O based on the following bus speeds:
66.7 MHz = 0.45 W (nominal), 0.5 W (maximum)
83.3 MHz = 0.5W (nominal), 0.6 W (maximum)
100 MHz = 0.6 W (nominal), 0.7 W (maximum)
Bus
(MHz)
CPM
Multiplication
Factor
CPM
(MHz)
CPU
Multiplication
Factor
CPU
(MHz)
P
INT
(W)
2,3
Vddl 1.5 Volts
Nominal
Maximum
66.67
2.5
166
3.5
233
0.95
1.0
66.67
2.5
166
4
266
1.0
1.05
66.67
3
200
4
266
1.05
1.1
66.67
3.5
233
4.5
300
1.05
1.15
83.33
3
250
4
333
1.25
1.35
83.33
3
250
4.5
375
1.3
1.4
83.33
3.5
292
5
417
1.45
1.55
100
3
300
4
400
1.5
1.6
100
3
300
4.5
450
1.55
1.65
1
These are typical values at 65 C. Impedance may vary by ±25% with process and temperature.
2
On silicon revision 0.0 (mask #: 0K49M), selectable impedance is not available. Impedance is set at 45
.
On all other revisions, impedance value is selected through the SIUMCR[20,21]. Refer to the
MPC8280 Addendum to
the MPC8260 PowerQUICC II Family Reference Manual
.
Output Buffers
Typical Impedance (
)
60x bus
45 or 27
2
Local bus
45
Memory controller
45 or 27
2
Parallel I/O
45
PCI
27
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