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參數(shù)資料
| 型號： | MPC826XAZUSPU |
| 廠商： | Motorola, Inc. |
| 英文描述： | MPC826xA (HiP4) Family Hardware Specifications |
| 中文描述： | MPC826xA（HiP4）家庭硬件規(guī)格 |
| 文件頁數(shù)： | 6/48頁 |
| 文件大?。?/td> | 315K |
| 代理商： | MPC826XAZUSPU |
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MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Features
– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and
user-de
fi
ned TDM serial interfaces
— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,
SCCs, SMCs, and serial channels
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
Additional features of the MPC826xA family are as follows:
CPM
— 32-Kbyte dual-port RAM
— Additional MCC host commands
— Eight transfer transmission convergence (TC) layers between the TDMs and FCC2 to support
inverse multiplexing for ATM capabilities (IMA) (MPC8264A and MPC8266A only)
CPM multiplexing
— FCC2 can also be connected to the TC layer.
TC layer (MPC8264A and MPC8266A only)
— Each of the 8 TDM channels is routed in hardware to a TC layer block
– Protocol-speci
fi
c overhead bits may be discarded or routed to other controllers by the SI
– Performing ATM TC layer functions (according to ITU-T I.432)
– Transmit (Tx) updates
– Cell HEC generation
– Payload scrambling using self synchronizing scrambler (programmable by the user)
– Coset generation (programmable by the user)
– Cell rate by inserting idle/unassigned cells
– Receive (Rx) updates
– Cell delineation using bit by bit HEC checking and programmable ALPHA and DELTA
parameters for the delineation state machine
– Payload descrambling using self synchronizing scrambler (programmable by the user)
– Coset removing (programmable by the user)
– Filtering idle/unassigned cells (programmable by the user)
– Performing HEC error detection and single bit error correction (programmable by user)
– Generating loss of cell delineation status/interrupt (LOC/LCD)
— Operates with FCC2 (UTOPIA 8)
— Provides serial loop back mode
— Cell echo mode is provided
— Supports both FCC transmit modes
– External rate mode—Idle cells are generated by the FCC (microcode) to control data rate.
– Internal rate mode (sub-rate)—FCC transfers only the data cells using the required data rate.
The TC layer generates idle/unassigned cells to maintain the line bit rate.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC826XAZUSPUX | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC826xA (HiP4) Family Hardware Specifications |
| MPC826XCVR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC⑩ II Integrated Communications Processor Hardware Specifications |
| MPC826XCZU | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC⑩ II Integrated Communications Processor Hardware Specifications |
| MPC826XVR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC⑩ II Integrated Communications Processor Hardware Specifications |
| MPC826XZU | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC⑩ II Integrated Communications Processor Hardware Specifications |
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