參數(shù)資料
型號(hào): MPC826XAZUSPU
廠商: Motorola, Inc.
英文描述: MPC826xA (HiP4) Family Hardware Specifications
中文描述: MPC826xA(HiP4)家庭硬件規(guī)格
文件頁(yè)數(shù): 13/48頁(yè)
文件大小: 315K
代理商: MPC826XAZUSPU
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
13
Electrical and Thermal Characteristics
All output pins on the MPC826xA have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized in order to minimize overdamped conditions and re
fl
ections caused by these
fast output switching times. This recommendation particularly applies to the address and data buses.
Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all
device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and
bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the V
CC
and GND circuits. Pull up all unused inputs or signals that will be inputs
during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.
Table 7 provides preliminary, estimated power dissipation for various con
fi
gurations. Note that suitable
thermal management is required for conditions above P
D
= 3W (when the ambient temperature is 70
C or
greater) to ensure the junction temperature does not exceed the maximum speci
fi
ed value. Also note that the
I/O power should be included when determining whether to use a heat sink.
1.2.4
AC Electrical Characteristics
The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and
inputs for the 66 MHz MPC826xA device. Note that AC timings are based on a 50-p
f
load. Typical output
buffer impedances are shown in Table 8.
Table 7. Estimated Power Dissipation for Various Configurations
1
1
Test temperature = room temperature (25
C)
2
P
INT
= I
DD
x V
DD
Watts
Bus
(MHz)
CPM
Multiplier
Core CPU
Multiplier
CPM
(MHz)
CPU
(MHz)
P
INT
(W)
2
Vddl 1.8 Volts
Vddl 2.0 Volts
Nominal
Maximum
Nominal
Maximum
66.66
2
3
133
200
1.2
2
1.8
2.3
66.66
2.5
3
166
200
1.3
2.1
1.9
2.3
66.66
3
4
200
266
2.3
2.9
66.66
3
4.5
200
300
2.4
3.1
83.33
2
3
166
250
2.2
2.8
83.33
2
3
166
250
2.2
2.8
83.33
2.5
3.5
208
291
2.4
3.1
Table 8. Output Buffer Impedances
1
1
These are typical values at 65 C. The impedance may vary
by ±25% with process and temperature.
Output Buffers
Typical Impedance (
)
60x bus
40
Local bus
40
Memory controller
40
Parallel I/O
46
PCI
25
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