參數(shù)資料
型號(hào): MPC826XAZUSPU
廠商: Motorola, Inc.
英文描述: MPC826xA (HiP4) Family Hardware Specifications
中文描述: MPC826xA(HiP4)家庭硬件規(guī)格
文件頁(yè)數(shù): 3/48頁(yè)
文件大小: 315K
代理商: MPC826XAZUSPU
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
3
Features
Figure 1 shows the block diagram for the HiP4 superset device, the MPC8266A.
Figure 1. MPC8266A Block Diagram
1.1
Features
The major features of the MPC826xA family are as follows:
Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 150–300 MHz
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— High-performance (6.6–7.65 SPEC95 benchmark at 300 MHz; 420 Dhrystones MIPS at
300 MHz)
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
Separate power supply for internal logic and for I/O
16 Kbytes
I-Cache
G2 Core
I-MMU
16 Kbytes
D-Cache
D-MMU
Communication Processor Module (CPM)
Timers
Parallel I/O
Baud Rate
Generators
32 Kbytes
Dual-Port RAM
32-bit RISC Microcontroller
and Program ROM
Serial
DMAs
4 Virtual
IDMAs
60x-to-PCI
Bridge
2,3
60x-to-Local
Bridge
Memory Controller
Clock Counter
System Functions
System Interface Unit
(SIU)
Local Bus
32 bits, up to 83 MHz
PCI Bus
2,3
32 bits, up to 66 MHz
or
MCC1
MCC2
FCC1
FCC2
FCC3
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I
2
C
Serial Interface
3 MII
Ports
2 UTOPIA
Ports
60x Bus
1. MPC8264A
2. MPC8265A
3. MPC8266A
Notes:
MiIMA
1,3
Interrupt
Controller
Time Slot Assigner
TC Layer Hardware
1,3
8 TDM Ports
Non-Multiplexed
I/O
Bus Interface Unit
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