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參數(shù)資料
| 型號： | MPC8245ARVV400D |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, LEAD FREE, TBGA-352 |
| 文件頁數(shù)： | 17/68頁 |
| 文件大?。?/td> | 1143K |
| 代理商： | MPC8245ARVV400D |
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MPC8245 Integrated Processor Hardware Specifications, Rev. 9
24
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 14 provides the AC test load for the MPC8245.
Figure 14. AC Test Load for the MPC8245
14b
sys_logic_clk to output high impedance (for all others)
—
4.0
ns
2
Notes:
1. All PCI signals are measured from GVDD/2 of the rising edge of PCI_SYNC_IN to 0.285 × OVDD or 0.615 × OVDD of the
signal in question for 3.3 V PCI signaling levels. See Figure 12.
2. All memory and related interface output signal specifications are specified from the VM = 1.4 V of the rising edge of the
memory bus clock, sys_logic_clk to the TTL level (0.8 or 2.0 V) of the signal in question. sys_logic_clk is the same as
PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every
rising and falling edge of PCI_SYNC_IN). See Figure 11.
3. PCI bused signals are composed of the following signals: LOCK, IRDY, C/BE[3:0], PAR, TRDY, FRAME, STOP, DEVSEL,
PERR, SERR, AD[31:0], REQ[4:0], GNT[4:0], IDSEL, and INTA.
4. To meet minimum output hold specifications relative to PCI_SYNC_IN for both 33- and 66-MHz PCI systems, the MPC8245
has a programmable output hold delay for PCI signals (the PCI_SYNC_IN to output valid timing is also affected). The initial
value of the output hold delay is determined by the values on the MCP and CKE reset configuration signals; the values on
these two signals are inverted and stored as the initial settings of PCI_HOLD_DEL = PMCR2[5, 4] (power management
configuration register 2 <0x72>), respectively. Since MCP and CKE have internal pull-up resistors, the default value of
PCI_HOLD_DEL after reset is 0b00. Further output hold delay values are available by programming the PCI_HOLD_DEL
value of the PMCR2 configuration register. Figure 15 shows the PCI_HOLD_DEL effect on output valid and hold times.
Table 11. Output AC Timing Specifications (continued)
Num
Characteristic
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
OVDD/2 for PCI
RL = 50 Ω
Output Measurements are Made at the Device Pin
GVDD/2 for Memory
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| MPC8245ARZU400D | 功能描述:微處理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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