參數(shù)資料
型號: MPC8241LZP166B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 166 MHz, RISC PROCESSOR, PBGA357
封裝: 25 X 25 MM, 1.27 MM HEIGHT, PLASTIC, BGA-357
文件頁數(shù): 46/64頁
文件大?。?/td> 827K
代理商: MPC8241LZP166B
50
MPC8241 Integrated Processor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
Figure 29. COP Connector Diagram
HRESET 7
HRST_CPU
HRST_CTRL
From Target
Board Sources
HRESET
13
SRESET 5
NC
11
VDD_SENSE
6
5 2
15 3
1 k
10 k
10 k
10 k
OVDD
CHKSTOP_IN 6
8
TMS
TDO
TDI
TCK
TMS
TDO
TDI
TCK
9
1
3
4
TRST
7
16
2
10
12
(if any)
COP
He
a
d
e
r
14 4
Key
Notes:
1. QACK is an output on the MPC8245 and is not required at the COP header for emulation.
2. RUN/STOP normally found on pin 5 of the COP header is not implemented on the MPC8245.
Connect pin 5 of the COP header to OVDD with a 1- k pull-up resistor.
3. CKSTP_OUT normally found on pin 15 of the COP header is not implemented on the MPC8245.
Connect pin 15 of the COP header to OVDD with a 10-k pull-up resistor.
4. Pin 14 is not physically present on the COP header.
QACK 1
OVDD
10 k
OVDD
TRST 7
10 k
OVDD
10 k
10 k
5. SRESET functions as output SDMA12 in extended ROM mode.
6. CHKSTOP_IN functions as output SDMA14 in extended ROM mode.
MPC8245
3
13
9
5
1
6
10
2
15
11
7
16
12
8
4
KEY
No pin
COP Connector
Physical Pin Out
1
7. The COP port and target board should be able to independently assert HRESET and TRST to
.
the processor in order to fully control the processor as shown above.
8. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the C
header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect
HRESET from the target source to TRST of the part through a 0-
isolation resistor.
0
8
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