參數(shù)資料
型號: MPC755BRX450LE
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 450 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁數(shù): 11/52頁
文件大?。?/td> 1278K
代理商: MPC755BRX450LE
19
MPC755 RISC Microprocessor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Figure 10 provides the AC test load for L2 interface of the MPC755.
Figure 10. AC Test Load for the L2 Interface
1.4.2.5
IEEE 1149.1 AC Timing Specifications
Table 13 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 12, Figure 13,
Table 13. JTAG AC Timing Specifications (Independent of SYSCLK) 1
At recommended operating conditions (see Table 3)
Parameter
Symbol
Min
Max
Unit
Notes
TCK frequency of operation
fTCLK
016
MHz
TCK cycle time
tTCLK
62.5
—ns
TCK clock pulse width measured at 1.4 V
tJHJL
31
ns
TCK rise and fall times
tJR, tJF
02
ns
TRST assert time
tTRST
25
ns
2
Input setup times:
Boundary-scan data
TMS, TDI
tDVJH
tIVJH
4
0
ns
3
Input hold times:
Boundary-scan data
TMS, TDI
tDXJH
tIXJH
15
12
ns
3
Valid times:
Boundary-scan data
TDO
tJLDV
tJLOV
4
ns
4
Output hold times:
Boundary-scan data
TDO
tJLDH
tJLOH
25
12
ns
4
TCK to output high impedance:
Boundary-scan data
TDO
tJLDZ
tJLOZ
3
19
9
ns
4, 5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-
load
(see Figure 11). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal which must be asserted for this minimum time to be recognized.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Output
Z0 = 50
L2OVDD/2
RL = 50
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