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參數資料
| 型號： | MPC7410VS450NE |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 4/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 450MHZ 360-FCCLGA |
| 標準包裝： | 44 |
| 系列： | MPC74xx |
| 處理器類型： | 32-位 MPC74xx PowerPC |
| 速度： | 450MHz |
| 電壓： | 1.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-CLGA，FCCLGA |
| 供應商設備封裝： | 360-FCCLGA（25x25） |
| 包裝： | 托盤 |
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MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
12
Freescale Semiconductor
Electrical and Thermal Characteristics
High-Z (off-state) leakage current,
Vin = L2OVDD/OVDD
1.8
ITSI
—20
A
2, 3,
5, 7
2.5
ITSI
—35
3.3
ITSI
—70
Output high voltage, IOH = –5 mA
1.8
VOH
(L2)OVDD – 0.45
—
V
8
2.5
VOH
1.7
—
3.3
VOH
2.4
—
Output low voltage, IOL = 5 mA
1.8
VOL
—0.45
V
8
2.5
VOL
—0.4
3.3
VOL
—0.4
Capacitance, Vin = 0 V, f = 1 MHz
Cin
—
6.0
pF
3, 4, 7
Notes:
1. Nominal voltages; see Table 3 for recommended operating conditions.
2. For processor bus signals, the reference is OVDD while L2OVDD is the reference for the L2 bus signals.
3. Excludes factory test signals.
4. Capacitance is periodically sampled rather than 100% tested.
5. The leakage is measured for nominal OVDD and L2OVDD, or both OVDD and L2OVDD must vary in the same
direction (for example, both OVDD and L2OVDD vary by either +5% or –5%).
6. Measured at max OVDD/L2OVDD.
7. Excludes IEEE 1149.1 boundary scan (JTAG) signals.
8. For JTAG support: all signals controlled by BVSEL and L2VSEL will see VIL/VIH/VOL/VOH/CVIH/CVIL DC limits of
1.8 V mode while either the EXTEST or CLAMP instruction is loaded into the IEEE 1149.1 instruction register by
the UpdateIR TAP state until a different instruction is loaded into the instruction register by either another UpdateIR
or a Test-Logic-Reset TAP state. If only TSRT is asserted to the part, and then a SAMPLE instruction is executed,
there is no way to control or predict what the DC voltage limits are. If HRESET is asserted before executing a
SAMPLE instruction, the DC voltage limits will be controlled by the BVSEL/L2VSEL settings during HRESET.
Anytime HRESET is not asserted (that is, just asserting TRST), the voltage mode is not known until either EXTEST
or CLAMP is executed, at which time the voltage level will be at the DC limits of 1.8 V.
Table 5. DC Electrical Specifications (continued)
At recommended operating conditions (see Table 3)
Characteristic
Nominal
Bus
Voltage1
Symbol
Min
Max
Unit
Notes
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