參數(shù)資料
型號(hào)： MPC7410VS450NE
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 35/56頁(yè)
文件大?。?/td> 0K
描述： IC MPU 32BIT 450MHZ 360-FCCLGA
標(biāo)準(zhǔn)包裝： 44
系列： MPC74xx
處理器類(lèi)型： 32-位 MPC74xx PowerPC
速度： 450MHz
電壓： 1.5V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 360-CLGA，F(xiàn)CCLGA
供應(yīng)商設(shè)備封裝： 360-FCCLGA（25x25）
包裝： 托盤(pán)
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
40
Freescale Semiconductor
System Design Information
the MPC7410 or by other receivers in the system. These signals can be pulled up through weak (10-k
Ω) pull-up
resistors by the system, address bus driven mode can be enabled (see the MPC7410 RISC Microprocessor Family
Users’ Manual for more information on this mode), or these signals may be otherwise driven by the system during
inactive periods of the bus to avoid this additional power draw. The snooped address and transfer attribute inputs
are: A[0:31], AP[0:3], TT[0:4], CI, WT, and GBL.
In systems where GBL is not connected and other devices may be asserting TS for a snoopable transaction while not
driving GBL to the processor, we recommend that a strong (1 k
Ω) pull-up resistor be used on GBL. Note that the
MPC7410 will only snoop transactions when GBL is asserted.
The data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not
require pull-up resistors on the bus. Other data bus receivers in the system, however, may require pull-ups, or that
those signals be otherwise driven by the system during inactive periods by the system. The data bus signals are:
DH[0:31], DL[0:31], and DP[0:7].
If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the
input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left
unconnected by the system. If parity checking is disabled through HID0, and parity generation is not required by the
MPC7410 (note that the MPC7410 always generates parity), then all parity pins may be left unconnected by the
system.
The L2 interface does not normally require pull-up resistors.
8.7 JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE
1149.1 specification, but is provided on all processors that implement the PowerPC architecture. While it is possible
to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset
performance will be obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is
also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not
practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated hardware
and debugging software) to access and control the internal operations of the processor. The COP interface connects
primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port
requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target
system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or
push-button switches, then the COP reset signals must be merged into these signals with logic.
The arrangement shown in Figure 25 allows the COP port to independently assert HRESET or TRST, while ensuring
that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be
tied to HRESET through a 0-
Ω isolation resistor so that it is asserted when the system reset signal (HRESET) is
asserted, ensuring that the JTAG scan chain is initialized during power-on. While Freescale recommends that the
COP header be designed into the system as shown in Figure 25, if this is not possible, the isolation resistor will allow
future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations.
The COP header shown in Figure 25 adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and can be as
inexpensive as an unpopulated footprint for a header to be added when needed.
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