參數(shù)資料
型號: MPC7410RX400LD
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁數(shù): 27/52頁
文件大?。?/td> 943K
代理商: MPC7410RX400LD
MOTOROLA
MPC7410 RISC Microprocessor Hardware Specifications
33
System Design Information
various example L2 clock frequencies that can be obtained for a given set of core frequencies. The minimum
L2 frequency target is 133 MHz. Sample core-to-L2 frequencies for the MPC7410 is shown in Table 14. In
this example, shaded cells represent settings that, for a given core frequency, result in L2 frequencies that
do not comply with the minimum and maximum L2 frequencies listed in Table 10.
1.8.2
PLL and DLL Power Supply Filtering
The AVDD and L2AVDD power signals are provided on the MPC7410 to supply power to the PLL and DLL,
respectively.
On systems that use the MPC7410 CBGA device, the L2AVDD filter should implement the circuit shown in
Figure 19. The AVDD filter on the MPC7410 CBGA device should implement the circuit shown in
On systems that use the MPC7410 HCTE device, the AVDD and L2AVDD input signals should both
implement the circuit shown in Figure 19.
The circuit shown below should be placed as close as possible to the AVDD pin to minimize noise coupled
from nearby circuits. A separate circuit should be placed as close as possible to the L2AVDD pin. It is often
possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the 360 CBGA
footprint, without the inductance of vias. The L2AVDD pin may be more difficult to route, but is
proportionately less critical.
It is the recommendation of Motorola, that systems that implement the AVDD filter shown in Figure 20
design in the pads for the removed capacitors (shown in Figure 19), to provide for the possible
reintroduction of the filter in Figure 19. This would be necessary in case there is a planned transition to the
HCTE package of the MPC7410.
Table 14. Sample Core-to-L2 Frequencies
Core Frequency
(MHz)
÷1
÷1.5
÷2
÷2.5
÷3
÷3.5
÷4
350
233
175
140
366
244
183
147
400
266
200
160
133
433
288
216
173
144
450
300
225
180
150
466
311
233
186
155
133
500
333
250
200
166
143
Note: The core and L2 frequencies are for reference only. Some examples may
represent core or L2 frequencies which are not useful, not supported, or not tested
L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK frequencies less
than 150 MHz.
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