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| 型號： | MPC7400RX400LX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 16/44頁 |
| 文件大小： | 744K |
| 代理商： | MPC7400RX400LX |
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MPC7400 RISC Microprocessor Hardware Specications
23
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Figure 11 provides the AC test load for TDO and the boundary-scan outputs of the MPC7400.
Figure 11. Alternate AC Test Load for the JTAG Interface
Figure 12 provides the JTAG clock input timing diagram.
Figure 12. JTAG Clock Input Timing Diagram
Valid Times:
Boundary-scan data
TDO
tJLDV
tJLOV
4
20
25
ns
4
Output Hold Times:
Boundary-scan data
TDO
tJLDX
tJLOX
TCK to output high impedance:
Boundary-scan data
TDO
tJLDZ
tJLOZ
3
19
9
ns
4,5
5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50 ohm load
(See Figure 11). Time-of-ight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Table 12. JTAG AC Timing Specifications (Independent of SYSCLK)1 (Continued)
At recommended operating conditions (See Table 3)
Parameter
Symbol
Min
Max
Unit
Notes
OUTPUT
Z0 = 50
OVdd/2
RL = 50
TCLK
VM
VM = Midpoint Voltage (OVDD/2)
tTCLK
tJR
tJF
tJHJL
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For More Information On This Product,
Go to: www.freescale.com
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