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參數(shù)資料
| 型號： | MPC7400RX400LX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 10/44頁 |
| 文件大?。?/td> | 744K |
| 代理商： | MPC7400RX400LX |
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18
MPC7400 RISC Microprocessor Hardware Specications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Figure 6 provides the input/output timing diagram for the MPC7400.
Figure 6. Input/Output Timing Diagram
1.4.2.3 L2 Clock AC Specications
The L2CLK frequency is programmed by the L2 Conguration Register (L2CR[4:6]) core-to-L2 divisor
ratio. See Table 15 for example core and L2 frequencies at various divisors. Table 10 provides the potential
range of L2CLK output AC timing specications as dened in Figure 7.
The L2SYNC_OUT signal is intended to be routed halfway out to the SRAMs and then returned to the
L2SYNC_IN input of the MPC7400 to synchronize L2CLKOUT at the SRAM with the processor’s internal
clock. L2CLKOUT at the SRAM can be offset forward or backward in time by shortening or lengthening
the routing of L2SYNC_OUT to L2SYNC_IN. See Motorola Application Note AN179/D “PowerPC
Backside L2 Timing Analysis for the PCB Design Engineer.”
SYSCLK
ALL INPUTS
VM
VM = Midpoint Voltage (OVDD/2)
tTSVKH
tARXKH
ALL OUTPUTS
tKHOX
VM
tKHDV
(Except TS, ABB,
ARTRY, DBB)
ALL OUTPUTS
TS,
ARTRY,
ABB/AMON(0),
(Except TS, ABB,
ARTRY, DBB)
DBB/DMON(0)
VM
tKHOE
tKHOZ
tKHABPZ
tKHARPZ
tKHARP
SHD1
SHD0,
tKHOV
tKHAV
tKHDX
tKHAX
tIXKH
tAXKH
tDVKH
tARVKH
tKHTSX
tKHTSV
tKHARV
tKHARX
tKHARV
tIVKH
tAVKH
tTSXKH
tDXKH
tKHDPV
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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